1. Filed of The invention
The present invention relates in general to a semiconductor package and a method for manufacturing such a package. Particularly, the present invention relates to a semiconductor package and a method for manufacturing such a package in which a semiconductor chip is connected to a plurality of inner leads of a lead frame having no paddle by means of soldering, thereby reducing the thickness of semiconductor package.
2. Description of the Prior Art
Recently, in correspondence with tendency of increasing the capacity of memory chip as the semiconductor techniques are substantially advanced, it is required to enclose a bare chip having a relatively huge size within a semiconductor package. Thus, the ratio of the area of the bare chip to the total area of the package is obliged to be increased.
Consequently, the increase of the relative area ratio mentioned above results in an increase in the volume of the semiconductor package, thereby inducing a problem in that a required size of the package can not be obtained.
Hence, there have been several efforts for solving the above problem, for example, an LOC (lead on chip) technique wherein leads are placed on the top of active semiconductor chip and, directly and electrically connected to the semiconductor chip. Here, a typical example of an SOJ (small outline J-lead) type of package according to the LOC technique will be described in conjunction with the accompanying drawings.
FIGS. 1 and 2 show a plane view of a wire bonding of a process for manufacturing the LOC-SOJ type of semiconductor package which is a representative example of 16MDRAM packages, and a sectional view showing a construction of a manufactured LOC-SOJ type of semiconductor package, respectively. As shown in the drawings, the LOC-SOJ type of package has a semiconductor chip 1 which is provided with insulating polyimide layers 2 coated on the opposite upper side surfaces thereof at a predetermined thickness throughout the whole length and width thereof. The chip 1 additionally includes a plurality of pads 3 each of which is electrically connected to an end of each inner lead 5 of a lead frame 4 through a wire 6 of which opposite ends are connected to the pad 3 and the inner lead 5, respectively. In addition, there is provided an epoxy resin layer 7 coated on a predetermined area including the chip 1 and the inner leads 5 of the frame 4 by a molding process.
In the drawings, the reference numerals, 5, 8 and 9, denote an outer lead of the lead frame, a damper and a support bar, respectively.
As described above, the LOC-SOJ type of package has an advantage in that it allows the inner leads 5 of the lead frame 4 to be pulled to an active cell of the semiconductor chip 1, thereby reducing the area wherein the inner leads 5 of the lead frame 4 occupy in the package.
However, the above LOC-SOJ type of package is obliged to be completely manufactured by an electric connection between the semiconductor chip 1 and the inner leads 5 of the lead frame 4 through the wires 5, thereby having a disadvantage in that it can only accomplish a limited thickness of the semiconductor package due to the electrical connection between the leads 5 and the chip 1.
In other words, a wire bonding is obliged to be performed for connecting the chip to leads in manufacturing the known semiconductor package, thus it is required to reduce a wire loop height as small as possible In order to accomplish the desired thickness. However, if the wire loop height is reduced as required, there may be a process and reliability problem such that the wire bonding is hard to achieve. In order to compensate such a problem, it is required both to select a wire material having a relatively higher strength sufficient for resisting the break of the wire and to develope a high quality wire bonding process to accomplish the reliable bonding of the wire.
Accordingly, it is inevitable that the known semiconductor package, for manufacturing a device where the wire bonding should be performed, is obliged to have a wire loop higher than the height of the inner lead 5 of the lead frame 4 irrespective of selected wire materials, thereby having a disadvantage in that it has an undesired substantial thickness.